The present disclosure relates to memory for an integrated circuit (IC) chip packaging, and more particularly to memory including a thermoelectric heat pump, an IC chip package including the memory and a related method.
IC chip packages may include a processor, such as an application specific IC (ASIC) chip, connected with a number of electrical interconnecting layers to scale the chip package for interconnection to other electrical devices. For example, many IC chip packages include a processor coupled by a number of micro-bumps to an interposer substrate, i.e., in 2.5D chip packaging technology. The interposer substrate may include a frontside metal interconnect layer, an interposer substrate including electrical interconnections, e.g., through silicon vias (TSVs), and a backside metal interconnect layer (e.g., a redistribution layer (RDL)). Each layer in the interposer substrate electrically connects to an adjacent layer to route electrical lines through the interposer substrate. The backside metal interconnect layer of the interposer substrate may connect to flip chip bumps, e.g., a controlled collapse chip connect (C4) layer, that connects to a laminated base substrate, e.g., printed wiring board (PCB), perhaps through a system-in-package (SiP) substrate. The base substrate can be connected to any variety of other electrical devices.
Certain types of IC chip packages include a processor integrated on an interposer substrate with another device such as a memory. One form of memory is a high bandwidth memory (HBM), which includes a three dimensional (3D) stacked, dynamic random access memory (DRAM). A memory is typically coupled to the interposer substrate and base substrate similarly to the processor. The memory is also operationally coupled to the processor. One challenge for an IC chip package including a processor and a memory is addressing mismatched operational temperatures of each device. For example, for a combined processor and memory chip package there is a significant mismatch in maximum junction temperature between the DRAM in the memory and the processor. For example, the memory may have a maximum junction temperature (Tj max) ranging from approximately 85° C. up to 105° C., but the processor may have a Tj max ranging up to 125° C. Furthermore, the processor may have an operational temperature range from −40° C. to 125° C., while the memory may have an operational temperature range from 0° C. and 85° C.
The operational temperature differentials can pose a number of challenges. For example, while the processor can operate at 125° C., the DRAM cell retention time decreases exponentially above approximately 85° C., greatly diminishing the performance of the memory. Similarly, the processor can operate below 0° C., but the memory needs to be heated above that temperature to operate. Other devices packaged with a processor can pose similar challenges due to operational temperature differences.
In most cases, heat dissipation is the only thermal issue addressed in IC chip packages. Heat dissipation is oftentimes addressed using a cover structure, which typically can take two forms: a lid or bare die. In either case, a heat sink is typically coupled to remove heat from the IC chip package. Where a lid is provided, it extends over the processor, and couples typically to the base substrate. Lids are advantageous because they allow one to handle the IC chip package with less concern about damage, and they reduce heat sink complexity. A heat sink is typically coupled to the lid using a thermal interface material (TIM) that acts to efficiently transfer heat to the heat sink to cool the IC chip package. While a lid thermally links the processor and the memory in the package, promoting heat transfer between the processor and the memory, they do not address all of the limitations posed by operational temperature differences. In other cases, a stiffener extends from the base substrate about the processor, leaving the processor and the memory thermally separated in the package. A heat sink may be coupled to an upper surface of the processor and/or the memory. The stiffener approach presents challenges because any heat sink used is more complex, and handling the IC chip package without damaging it is more cumbersome. The stiffener, like the lid, also does not address all of the limitations posed by operational temperature extremes of the processor and the memory in the IC chip package.
One approach to address operational temperature differences employs a thermoelectric cooling device configured to thermally control the memory in response to a predicted change in temperature of the memory. In this case, a heat spreader is mounted to the memory, the thermoelectric cooler is positioned on the heat spreader, and a heat sink is mounted on the thermoelectric cooler. The thermoelectric cooler is controlled via electrical connections directly thereto from a separate power manager. This approach is cumbersome to build.